1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an EPROM (erasable programmable read-only memory) which is electrically programmable and of which stored data can be erased by ultraviolet rays.
2. Description of the Related Art
An EPROM of which stored data can be erased by ultraviolet rays is generally known as one of electrically programmable non-volatile MOS type semiconductor memories.
FIG. 3 shows the sectional structure of a known EPROM provided with a floating gate. In FIG. 3, symbol A denotes a region in which a memory cell is formed to store data, and symbol B denotes a region in which a decoder transistor is formed to selectively apply a voltage to the control gate of the memory cell.
The EPROM is generally formed of an N-channel MOS in which a memory cell, a decoder transistor, and the like, are formed on a P conduction type semiconductor substrate 10. Actually, memory cells are arranged in a matrix and decoders are arranged around the matrix to select the memory cells.
The memory cell formed in the region A comprises a floating gate 11 for storing electrons, source (S) and drain (D) regions 12 and 13 formed of N.sup.+ diffused layers highly doped with N conduction type impurities and introducing hot electrons in the substrate 10 in programming, a thin gate oxide film 14 capable of passing the hot electrons, a control gate (CG) 15 to which a voltage is applied in reading data, and an interlayer insulating film 16 for isolating the floating gate 11 from the control gate 15 and serving as a dielectric layer constituting a coupling capacitor between the gates 11 and 15. Generally, a silicon oxide film (SiO.sub.2) formed by thermal oxidation and CVD technique has been used conventionally as this interlayer insulating film 16.
The decoder transistor formed in the region B comprises source (S) and drain (D) regions 17 and 18 which are formed of N.sup.+ diffused layers highly doped with N conduction type impurities, a gate electrode (G) 19 and a gate oxide film 20 for gate isolation.
The control gate 15 of the memory cell is connected with the drain (D) 18 of the decoder transistor so that the decoder transistor selectively applies a voltage to the control gate 15 of the memory cell. Incidentally, the substrate is generally grounded.
In the EPROM constructed as described above, writing of data is carried out in such a way that hot electrons are generated in the neighborhood of the drain by applying a high voltage of 10-15 V between the source and drain of the programmable memory cell, and a voltage is applied to the floating gate 11 to inject the hot electrons thus generated into the floating gate 11. On the other hand, erasing of data is performed by irradiating ultraviolet rays onto the floating gate 11 through a quartz window provided in a package (not shown) so that the electrons in the floating gate 11 vanish.
In recent years, in order to improve the breakdown voltage characteristic between the floating gate 11 and the control gate 15 of the memory cell and reliability thereof in the EPROM as described above, the interlayer insulating film 16 is formed of, in place of the conventional oxide film in many cases, a three-layer film (hereinafter referred to as ONO film) including three layers of an oxide film (Si0.sub.2), a nitride film (Si.sub.3 N.sub.4) and an oxide film (SiO.sub.2).
In the case where the ONO film is used as the interlayer 16 between the floating gate 11 and the control gate 15, if a voltage V.sub.CG is applied to the control gate 15 when collectively erasing stored data by ultraviolet rays, the control characteristic of the memory cell after the data have been erased changes so that the threshold voltage V.sub.TH of the control gate 15 also changes in accordance with the applied voltage V.sub.CG. This is disclosed in e.g. "Polyoxide Thinning Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory Devices", by Seiich Mori et al, IEEE Transaction on Electron Devices, Vol. 38, No. 2, February 1991, pp. 270 -277. As seen from FIG. 4 showing the control voltage V.sub.CG in data erasing and the threshold value V.sub.TH of the control voltage after data erasure, if a silicon oxide film is used as the interlayer insulating film 16, the threshold voltage V.sub.TH is fixed regardless of the magnitude of the control voltage V.sub.CG ; in contrast, if the ONO film is used, the threshold voltage lowers with lowering of control voltage V.sub.CG. Since the data erasure has conventionally been made without applying a voltage to the control gate 15, the threshold voltage after the data erasure is 1.5 V or so even when the ONO film is used like an the case where the silicon oxide film is used.
When the EPROM is used with the power supply voltage of an ordinary 5 V series, no problem occurs. However, when the EPROM is used with a product operating with a low voltage battery of a 1.5 V series, it is required to reduce the threshold voltage. Therefore, it would be considered to apply a negative voltage to the control gate 15 in data erasing thereby to reduce the threshold voltage after data erasure to about 1-0.5 V by utilizing the characteristic of the ONO film as shown in FIG. 4. By reducing the threshold voltage to this degree, the EPROM can be operated with the battery of the 1.5 V series.
In the conventional EPROM having the sectional structure as shown in FIG. 3, the control voltage applied to the control gate of the memory cell by using a decorder transistor must be positive relative to the potential of the substrate 10. More specifically, if the control voltage were negative relative to the substrate 10, the junction between the P type substrate and the N type drain 18 should be forward-biased so that it is not allowed to apply a negative voltage to the control gate. Thus, the conventional EPROM involves a problem that in data erasing, the negative voltage cannot be applied to the control gate 15.